Q1.An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped
I/O as show in the figure. The address lines A0 and A1 of the 8085 are used
by the 8255 chip to decode internally its thee ports and the Control register.
The address lines A3 to A as well as the signal are used for address
decoding. The range of addresses for which the 8255 chip would get selected is
Q4.A load is supplied by a 230 V, 50 Hz source. The active power P and the reactive power Q consumed by the load are such that 1 kW ≤ P ≤ 2kW and 1kVAR ≤ Q ≤ kVAR . A capacitor connected across the load for power factor correction generates 1 kVAR reactive power. The worst case power factor after power factor correction is
For the NMOSFET in the circuit shown, the threshold voltage is Vth, where Vth > 0. The source voltage VSS is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as a function VSS is represented by
Answer : Option AExplaination / Solution:
We have the following conditions
Since it is in saturation, current ID is given by
Thus, ID - VSS graph shows Parabolic relation for Vss < VDD
- Vth and zero for Vss > VDD
- Vth. Only graph shown in option (A) satisfies this result.