Electronic Devices - Online Test
Q1. The channel resistance of an N-channel JFET shown in the figure below is 600Ω when the full channel thickness (tch) of 10μm is available for conduction. The
built-in voltage of the gate P+ N junction (Vbi) is -1 V. When the gate to source
voltage (VGS) is 0 V, the channel is depleted by 1 μm on each side due to the built
in voltage and hence the thickness available for conduction is only 8 μm
The channel resistance when VGS = -3 V is
Answer : Option B
Explaination / Solution:
Q2. The channel resistance of an N-channel JFET shown in the figure below is 600Ω when the full channel thickness (tch) of 10μm is available for conduction. The built-in voltage of the gate P+ N junction (Vbi) is -1 V. When the gate to source voltage (VGS) is 0 V, the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm
The channel resistance when VGS = 0 V is
Answer : Option C
Explaination / Solution:
Q3. 
The bias current IDC through the diodes is
Answer : Option A
Explaination / Solution:
The current flows in the circuit if all the diodes are forward biased. In forward biased there will be 0 7. V drop across each diode.
Q4. 
The ac output voltage Vac is
Answer : Option B
Explaination / Solution:
The forward resistance of each diode is
Q5. A small percentage of impurity is added to an intrinsic semiconductor at 300 K. Which one of
the following statements is true for the energy band diagram shown in the following figure?
Answer : Option A
Explaination / Solution:
New energy level is near to conduction band, so it is pentavalent atoms to form n-type semiconductor.
Q6. Consider the following statements for a metal oxide semiconductor field effect transistor
(MOSFET):
P: As channel length reduces, OFF-state current increases.
Q:As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.
Which of the above statements are INCORRECT?
Answer : Option C
Explaination / Solution:
Q7. What is the voltage Vout in the following circuit?
Answer : Option C
Explaination / Solution:
The transfer characteristics of the CMOS inverter is as follows
Since the inverter is connected in feedback loop formed by connecting
10XΩ resistor between
the output and input, the output goes and stays at the middle of the characteristics
Va Switching threshold of inverter
Q8. Consider a silicon sample at T=300K, with a uniform donor density 
illuminated uniformly such that the optical generation rate
is 
throughout the sample. The incident radiation is turned off at 𝑡=0.
Assume low-level injection to be valid and ignore surface effects. The carrier lifetimes are 
illuminated uniformly such that the optical generation rate
is throughout the sample. The incident radiation is turned off at 𝑡=0.
Assume low-level injection to be valid and ignore surface effects. The carrier lifetimes are The hole concentration at t = 0 and the hole concentration at t = 0.3μs, respectively, are
Answer : Option A
Explaination / Solution:
Q9. In the circuit shown below, the knee current of the ideal Zener dioide is 10 mA
. To maintain 5 V across RL, the minimum value of RL in Ω and the minimum
power rating of the Zener diode in mW, respectively, are
Answer : Option B
Explaination / Solution:
No Explaination.
Q10. The small-signal resistance 
in kW offered by the n-channel
MOSFET M shown in the figure below, at a bias point of VB = 2V is (device
data for M: device transconductance parameter 
, threshold voltage VTN = 1V, and neglect body effect and channel length
modulation effects)
in kW offered by the n-channel
MOSFET M shown in the figure below, at a bias point of VB = 2V is (device
data for M: device transconductance parameter , threshold voltage VTN = 1V, and neglect body effect and channel length
modulation effects)
Answer : Option A
Explaination / Solution:
No Explaination.
