Digital Circuits - Online Test
Q1. The output Y in the circuit below is always ‘1’ when
Answer : Option B
Explaination / Solution:
The given circuit is shown below:
If any two or more inputs are ‘1’ then output y will be 1.
Q2. When the output Y in the circuit below is ‘1’, it implies that data has
Answer : Option A
Explaination / Solution:
No Explaination.
Q3. The logic function implemented by the circuit below is (ground implies logic 0)
Answer : Option D
Explaination / Solution:
Q4. The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to
analog (D/A) converter as shown in the figure below. Assume all the states
of the counter to be unset initially. The waveform which represents the D/A
converter output v0 is
Answer : Option A
Explaination / Solution:
All the states of the counter are initially unset.
State Initially are shown below in table:
Q2Q1Q0
0 0 0 0
1 0 0 4
1 1 0 6
1 1 1 7
0 1 1 3
0 0 1 1
0 0 0 0
Q5. Two D flip-flops are connected as a synchronous counter that goes through the
following QBQA sequence 00⟶11⟶01⟶10⟶00⟶… The combination to the inputs DA and DB are
Answer : Option D
Explaination / Solution:
The sequence is QBQA
00⟶11⟶01⟶10⟶00⟶…
Q6. An 8085 assembly language program is given below. Assume that the carry
flag is initially unset. The content of the accumulator after the execution of the
program is
Answer : Option C
Explaination / Solution:
Initially Carry Flag, C = 0
MVI A, 07 H ; A = 0000 0111
RLC ; Rotate left without carry. A = 00001110
MVO B, A ; B = A = 00001110
RLC ; A = 00011100
RLC ; A = 00111000
ADD B ; A = 00111000
; +00001110
; 01000110
RRC ; Rotate Right with out carry, A = 0010 0011
Thus A = 23 H
Q7. The first six points of the 8-point DFT of a real valued sequence are 5, 1 - j3, 0, 3 - 4j, 0 and 3 + 4j .....The last two points of the DFT are respectively
Answer : Option B
Explaination / Solution:
For 8 point DFT, 
and it is conjugate
symmetric about x[4], x[6] = 0; x[7] = 1 + j3
and it is conjugate
symmetric about x[4], x[6] = 0; x[7] = 1 + j3
Q8. The output of the combinational circuit given below is
Answer : Option C
Explaination / Solution:
Q9. Identify the circuit below.
Answer : Option A
Explaination / Solution:
No Explaination.
Q10. The functionality implemented by the circuit below is
Answer : Option B
Explaination / Solution:
Decoder inputs will behaves as MUX select lines and when the output of decoder is high then only corresponding buffer will be enable and passed the inputs (P,Q,R,S) to the outpuut line, so it will work as 4-to-1 multiplexer.
