EC GATE 2010 - Online Test
Q1. 
In the circuit shown, all the transmission line sections are lossless. The Voltage Standing Wave Ration(VSWR) on the 60 Ω line is
Answer : Option B
Explaination / Solution:
Q2. 
Consider a baseband binary PAM receiver shown below. The additive channel noise n(t) is with power spectral density 
The lowpass filter is ideal with unity gain and cut-off frequency 1 MHz. Let Yk represent the random variable y(tk).
The lowpass filter is ideal with unity gain and cut-off frequency 1 MHz. Let Yk represent the random variable y(tk).Yk = Nk , if transmitted bit bk = 0
Yk = a + Nk if transmitted bit bk = 1
Where Nk represents the noise sample value. The noise sample has a probability density function, 
(This has mean zero and variance 2/α2). Assume transmitted bits to be equiprobable and threshold z is set to a/2
= 10-6 V.
(This has mean zero and variance 2/α2). Assume transmitted bits to be equiprobable and threshold z is set to a/2
= 10-6 V.The value of the parameter α
(in V-1) is
Answer : Option B
Explaination / Solution:
Let response of LPF filters
Noise variance (power) is given as
Q3.
Consider a baseband binary PAM receiver shown below. The additive channel noise n(t) is with power spectral density The lowpass filter is ideal with unity gain and cut-off frequency 1 MHz. Let Yk represent the random variable y(tk).
The lowpass filter is ideal with unity gain and cut-off frequency 1 MHz. Let Yk represent the random variable y(tk).Yk = Nk , if transmitted bit bk = 0
Yk = a + Nk if transmitted bit bk = 1
Where Nk represents the noise sample value. The noise sample has a probability density function, (This has mean zero and variance 2/α2). Assume transmitted bits to be equiprobable and threshold z is set to a/2 = 10-6 V.
(This has mean zero and variance 2/α2). Assume transmitted bits to be equiprobable and threshold z is set to a/2 = 10-6 V.The probability of bit error is
Answer : Option D
Explaination / Solution:
Probability of error is given by
Q4. Match the logic gates in Column A with their equivalents in Column B
Answer : Option D
Explaination / Solution:
Q5. 
For the output F to be 1 in the logic circuit shown, the input combination should be
Answer : Option C
Explaination / Solution:
Q6. In the circuit shown, the device connected Y5 can have address in the range
Answer : Option B
Explaination / Solution:
Q7. 
Assuming that the flip-flop are in reset condition initially, the count sequence observed at QA, in the circuit shown is
Answer : Option D
Explaination / Solution:
Q8. The Boolean function realized by the logic circuit shown is
Answer : Option D
Explaination / Solution:
Output of the MUX can be written as
Q9. 
For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is
Answer : Option C
Explaination / Solution:
By executing instruction one by one
Q10. The transfer function Y(s)/R(s) of the system shown is
Answer : Option B
Explaination / Solution:
