Q5.A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID),
Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages.
The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO
stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL
instruction, and 6 clock cycles for DIV instruction respectively. Operand
forwarding is used in the pipeline. What is the number of clock cycles needed to
execute the following sequence of instructions?
Answer : Option AExplaination / Solution: No Explaination.
Q6.One of the header fields in an IP datagram is the Time to Live (TTL) field. Which
of the following statements best explains the need for this field?
Answer : Option BExplaination / Solution: No Explaination.
Q8.Consider the methods used by processes P1 and P2 for accessing their critical
sections whenever needed, as given below. The initial values of shared boolean
variables S1 and S2 are randomly assigned.
Which one of the following statements describes the properties achieved?
Answer : Option BExplaination / Solution: No Explaination.
Q9.Which of the following concurrency control protocols ensure both conflict
serializability and freedom from deadlock?
I. 2-phase locking II. Time-stamp ordering
Answer : Option AExplaination / Solution: No Explaination.